A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems. In particular, flash memory is a type of electronic memory media that can be rewritten and retain content without consumption of power. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors. Flash memory technology can include NOR flash and/or NAND flash, for example. NOR flash evolved from electrically erasable read only memory (EEPROM) chip technology, in which, unlike flash, a single byte can be erased; and NAND flash evolved from DRAM technology. Flash memory devices can be less expensive and denser as compared to many other memory devices, meaning that flash memory devices can store more data per unit area.
Flash memory has become popular, at least in part, because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be used in many portable electronic products, such as cellular phones, computers, voice recorders, thumbnail drives, and the like, as well as in many larger electronic systems, such as automobiles, airplanes, industrial control systems, etc. The fact that flash memory can be rewritten as well as its retention of data without a power source, small size and light weight have all combined to make flash memory devices a useful and popular means for transporting and maintaining data.
Flash memory typically comprises an array of nonvolatile memory cells wherein data (e.g., one or more bits of data) can be stored. One type of flash memory comprises multi-level memory cells (e.g., quad-level memory cells) where each level can be associated with a respective data state. The multi-level memory cells also can comprise more than one memory element in which data can be stored. For example, a quad-level flash memory cell can comprise two memory elements that each can be programmed to four levels resulting in a memory cell that can have sixteen available data states and can store four bits of data. Each level of a multi-level memory cell can have a respective region or window that is associated with a respective data state.
Typically, memory cells can be formed in an array comprising wordlines (WLs) and bitlines (BLs) formed into an array, where memory cells can be located at points where the WLs and BLs intersect. The WLs can be respectively connected with gates of memory cells, and the respective drains and sources of memory cells can be connected with respective BLs. To perform operations, such as program, read, verify, or erase, on memory cells, a desired gate voltage, drain voltage, and source voltage can be applied to a memory cell via the WL and BLs, respectively, to effect the desired operation.
As density of memory devices have increased, spacing between adjacent WLs has become more narrow and the width of WLs has become more narrow. As a result, during read and verify operations when a WL and associated memory cell is selected for the read or verify operation, WLs adjacent to the WL selected can cause bit disturb to the selected memory cell, as it can shift the threshold voltage (Vt) and drain-source current (Ids) of the selected memory cell, based in part on the programming state of the adjacent memory cells associated with the adjacent WLs. For instance, when the adjacent memory cells are programmed, an undesirable electric field can be generated by the adjacent WLs, based in part on the programmed state of the adjacent memory cells, and this undesirable electric field can reach the selected WL and/or associated selected memory cell and can cause a shift in the Vt and narrow the operation window of the selected memory cell. Also, during a read or verify operation associated with a selected memory cell and WL, when the adjacent memory cells are not programmed (e.g., in an erase state), an undesirable fringing current can flow under and outside the selected WL, and this undesirable fringing current can cause a shift in the Vt (and a corresponding shift in the drain-source current (Ids)) and narrow the operation window of the selected memory cell. It is desirable to efficiently minimize or reduce adjacent wordline disturb and maintain a desirable operation window in memory cells.